GIF89a; EcchiShell v1.0
//proc/self/root/usr/include/pgsql/ 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) /* * If we're on GCC 4.1.0 or higher, we should be able to get a memory * barrier out of this compiler built-in. But we prefer to rely on our * own definitions where possible, and use this only as a fallback. */ #define pg_memory_barrier() __sync_synchronize() #endif #elif defined(__ia64__) || defined(__ia64) #define pg_compiler_barrier() _Asm_sched_fence() #define pg_memory_barrier() _Asm_mf() #elif defined(WIN32_ONLY_COMPILER) /* Should work on both MSVC and Borland. */ #include #pragma intrinsic(_ReadWriteBarrier) #define pg_compiler_barrier() _ReadWriteBarrier() #define pg_memory_barrier() MemoryBarrier() #endif /* * If we have no memory barrier implementation for this architecture, we * fall back to acquiring and releasing a spinlock. This might, in turn, * fall back to the semaphore-based spinlock implementation, which will be * amazingly slow. * * It's not self-evident that every possible legal implementation of a * spinlock acquire-and-release would be equivalent to a full memory barrier. * For example, I'm not sure that Itanium's acq and rel add up to a full * fence. But all of our actual implementations seem OK in this regard. */ #if !defined(pg_memory_barrier) #define pg_memory_barrier() \ do { S_LOCK(&dummy_spinlock); S_UNLOCK(&dummy_spinlock); } while (0) #endif /* * If read or write barriers are undefined, we upgrade them to full memory * barriers. * * If a compiler barrier is unavailable, you probably don't want a full * memory barrier instead, so if you have a use case for a compiler barrier, * you'd better use #ifdef. */ #if !defined(pg_read_barrier) #define pg_read_barrier() pg_memory_barrier() #endif #if !defined(pg_write_barrier) #define pg_write_barrier() pg_memory_barrier() #endif #endif /* BARRIER_H */